One sentence becomes a typed spec.

A deterministic extractor reads every number and unit in English or Chinese. No language model writes numbers. ChipLaya v1.0.1 answers only closed questions: the family and the goal; the architecture and its sub-blocks; what each number specifies, and whether it is a lower or upper limit.

ChipLaya is our decision model: Laya by Convai Innovations, run through a PyTorch port of Laya-MLX and fine-tuned for circuit design (model repository ↗). The op-amp questions use its pinned tensors and the new questions use the v2 agent tensors. Every answer is combined with a rule prior, and the spec lists every default it filled in.

Search where the physics allows.

Every buildable architecture becomes an arm, and analytic models screen out provably infeasible ones. An asynchronous engine runs up to 12 ngspice workers with warm starts from analytic optima; Gaussian-process proposals inside trust regions; a fidelity ladder that promotes promising designs from cheap working benches to sign-off (corners, Monte Carlo, full ADC records); repairs ranked by ChipLaya; successive halving across arms; scouting of other structures once a feasible design exists; and stop rules for convergence and budget.

ADCs are designed hierarchically: comparator and sampler blocks are searched against budgets derived from the ADC spec.

Real tools, honest results.

A design counts only when it passes at its sign-off fidelity. Every family then shows its design as xschem schematics, checked against the netlist the engine simulated, and as Magic layouts with DRC, LVS, extraction and post-layout simulation. Op-amps run the ChipLaya-guided Magic layout loop with RC extraction and post-layout ngspice. Comparators and sampling switches get one Magic cell, whose extracted netlist is simulated again at tt; a design that misses a limit there is reported as "layout failed". SAR and flash ADCs are drawn block by block (comparator, sampler, CDAC and SAR logic, or the comparator row and the resistor ladder) and assembled; DRC and LVS check the whole hierarchy, and the s3 conversion bench runs again on the extracted netlist. The flash encoder is not drawn: the signed-off netlist decodes the thermometer code in Python (behavioural), so the comparator outputs are the layout's ports.

The experimental LDO, active-filter, DAC and integer-N ring PLL examples use transistor netlists, xschem, Magic DRC, Netgen LVS and extracted-circuit simulation. References, bias and loads are external. PLL lock is checked in the complete transistor loop; random jitter, phase noise and mismatch yield are not measured. A missing measurement cannot satisfy a requested limit.

When the design loop stops at its budget without a qualified design, ChipJev still draws, checks and extracts the least-violating one and says where it stands. A run stops at 30 minutes at most; most take 1–8 minutes. You can download the spec, decisions, engine trace, netlists, xschem sheets, testbenches and layouts of the current run.